Work around for generating particular code using generate block with dynamic variable in SVA for assert property

SystemVerilog
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7

Hello Ben,
Thanks for your reply,

Here length and tag value changes with the cmd_valid, for every cmd_valid those both tag and length values will change.

I have used previously by keeping only for loop, I am getting Below error


   always @(posedge cmd_valid) begin
      if(cmd_type == 0 && cmd_last == 1) begin
           for(int i = 0; i <= (length/(READ_DATA/8)); i++) begin
               property_a: assert property (P_TAG_CHECK(tag))
	         else $error("ERROR");
            end
       end
   end

Error-[V2KGEUV] Unknown or bad value for genvar
/src/assertions/mim_bfm_assertions.sv, 659
  Instance/Generate block name: test_tb.tes_if.u_test_assert
  Elaboration time unknown or bad value encountered for generate for-statement
  condition expression.
  Please make sure it is elaboration time constant.