Work around for generating particular code using generate block with dynamic variable in SVA for assert property

SystemVerilog
, , , ,
5

Hello Ben,

This is the assertion I have written previously,


property P_TAG_CHECK(tag);  
		@(posedge rd_rsp_clk) disable iff (rst_n !== 1)
		rdata_valid ##0 ((rdata_tag == tag) && (rdata_error == 0 || rdata_error == 1));		
endproperty: P_TAG_CHECK

// length(signal) is the signal changes with every command valid
// parameter READ_DATA = 32;
// tag is some value

always @(posedge cmd_valid) begin
      if(cmd_type == 0 && cmd_last == 1) begin
           for(genvar i = 0; i <= (length/(READ_DATA/8)); i++) begin
               property_a: assert property (P_TAG_CHECK(tag))
	         else $error("ERROR");
            end
       end
   end

I am using this genvar approach, it is throwing error(Because of dynamic variable) any work around for that (or) any other approach for this scenario.

My intension is to generate assert properties based on the condition of length/(DATA_WIDTH/8).

Thanks,
Pavan.