Within ' disable iff ( ! reset ) , is the reset synchronous OR asynchronous?

SystemVerilog
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2

In reply to hisingh:
The disable iff ( ! reset ) is asynchronous.
From my SVA book:
To provide a synchronous abort, three not identical options with specific implications can be used: 1) With the sync_accept_on (see 3.9.14); for example:


ap_sync: assert property(@ (posedge clk)
   sync_accept_on (!rst_n) // If rst_n==0 then assertion is vacuously true
     a |-> ##3 b);
  1. With a sampled valued function (see 4.2.1.2); for example :

ap_dis_sync: assert property(@ (posedge clk) // If synchronous fell(rst_n)
   disable iff ($fell(!rst_n, @(posedge clk))) // then assertion is cancelled
     a |-> ##3 b);
/* Note that this approach is not always ideal, particularly for designs where the reset signal is active low and is generated from a power supply circuit and is maintained in the zero state until the supply voltage is stable (e.g., at 5V). In this case, there is no $fell(!rst_n); $rose(!rst_n) would work, but any future resets would be problematic since they would not emulate RTL logic.*/
  1. With the triggered of a sequence; for example:

sequence qSoftReset2; @ (posedge clk) $rose(soft_hardware_reset_command) ##1 ack;
endsequence : qSoftReset2
apTest: assert property (
    @ (posedge clk) disable iff (qSoftReset2.triggered)
     a |=> b);

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…

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