Will forcing an assigned wire also force the assignee?

SystemVerilog
1 
wire a;
wire b;
assign a = b;

Will

force a=1;

also force b to 1?

2

I ran this code:

module top;
 	wire a;
	wire b;
	assign a = b;
  initial begin
    force a = 1;
    #100;
    $display("a=%b", a);
    $display("b=%b", b);
  end
endmodule

The output is:

a=1
b=z

So I think the answer is no, it won’t force b to 1.

3

In reply to kjhhgt76:

A continuous assign statement is unidirectional. The flow of data is always from RHS to LHS of the assignment.

The same cannot be said about a port connection when both sides of the connection are nets.

module top;
  wire a=1;
  bot inst(.b(a));
    initial begin
      #1 $display("a: %b",a);
      force inst.b = 0;
      #5 $display("a: %b",a);
    end
endmodule

module bot(input wire b);
  initial begin
    #1 $display("b: %b",b);
    #5 $display("b: %b",b);
  end
endmodule

The wires a and b get collapsed into a single net.

4

In reply to dave_59:

The output of your code is

a: 1
b: 0
a: 0
b: 0

not

a: 1
b: 1
a: 0
b: 0

why?

5

In reply to kjhhgt76:

THere are race conditions in my code between the two initial blocks. You get different results depending on which tool you try. Changing the first #1 to a #2 removes the races.

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