Will forcing an assigned wire also force the assignee?

SystemVerilog
2

I ran this code:

module top;
 	wire a;
	wire b;
	assign a = b;
  initial begin
    force a = 1;
    #100;
    $display("a=%b", a);
    $display("b=%b", b);
  end
endmodule

The output is:

a=1
b=z

So I think the answer is no, it won’t force b to 1.