Why `uvm_info return meaningless instance name/

UVM
,
1

Hi,

I am using `UVM_INFO(get_type_name(), “build()…”, UVM_LOW)") to trace the simualtion.

The simulation log looks weired.

Why the component become COMP_343, COMP_352, which are supposed to be test1, pkt_env?

UVM_INFO tb.sv(143) @ 0: COMP_343 [test1] build()…
UVM_INFO tb.sv(71) @ 0: COMP_343.COMP_352.m_drv [pkt_driver] pkt_driver: connect_phase()…

Thanks,
Tom

2

If the component is a parameterized class, then there is no type name string associated with the object.

I do not use get_type_name or get_name when printing messages. The full pathname of the component is already included. I prefer to use a unique code that can be used to control the message later if needed.

3

In reply to dave_59:

Thank Dave.

I don’t think the component is a parameterized class.

class pkt_env extends uvm_env;
    pkt_sequencer m_seqr;
    pkt_sequence m_seq;
    pkt_driver m_drv;
    
    `uvm_component_utils(pkt_env)
    
    function new(name, uvm_component parent);
        super.new(name, parent);
        m_seqr = pkt_sequencer::type_id::create("m_seqr", this);
        m_seq = pkt_sequence::type_id::create("m_seq");
        m_drv = pkt_driver::type_id::create("m_drv", this);
    endfunction

    virtual function void connect_phase(uvm_phase phase);
        super.connect_phase(phase);
        //uvm_report_info(get_type_name(), "connect_phase()...", UVM_LOW);
        //`uvm_info(get_type_name(), "connect_phase()...", UVM_LOW)
        **$display({"pkt_env: ", get_full_name()});**
        m_drv.seq_item_port.connect(m_seqr.seq_item_export);
    endfunction

endclass

In log:
pkt_env: COMP_345.COMP_354

4

In reply to mlsxdx:

Your problem is that you are not assigning names to your components when constructing them. The COMP_1234 names are created so that the testbench hierarchy can be properly constructed. You did this properly for driver and sequencer, but I’m guessing you did not do this for the pkt_env and test. Try this example

import uvm_pkg::*;
`include "uvm_macros.svh"
class pkt_env extends uvm_env;
   `uvm_component_utils(pkt_env) 
     function new(string name, uvm_component parent);
        super.new(name, parent);
     endfunction
   virtual function void connect_phase(uvm_phase phase);
      `uvm_info(get_type_name(), "connect_phase() type name", UVM_LOW)
      `uvm_info(get_full_name(), "connect_phase() full name", UVM_LOW)
      $display({"full name: ", get_full_name()});
   endfunction
   
endclass : pkt_env

module top;
   pkt_env p1,p2;
   
   initial begin
      p1 = new("p1", null);
      p1.connect_phase(null);
      p2 = new("", null); // no name
      p2.connect_phase(null);
   end
endmodule : top
5

In reply to dave_59:

Thanks, Dave. You are right.

Look at the function new(), name should be string name; otherwise, pkt_env name will uses default - COMP_354.

Tom

6

In reply to mlsxdx:

I got a compiler error with just ‘name’. I thought that was just a copy paste typo. It should have failed because ‘name’ will get defined as a 1-bit logic by default and the call to super.new(name,parent) will be trying to assign a 1-bit logic to a string, which is illegal according to the SystemVerlog LRM

7

In reply to dave_59:

Different compiler check differently. NCSIM doesn’t throw any error.