In reply to mlsxdx:
Your problem is that you are not assigning names to your components when constructing them. The COMP_1234 names are created so that the testbench hierarchy can be properly constructed. You did this properly for driver and sequencer, but I’m guessing you did not do this for the pkt_env and test. Try this example
import uvm_pkg::*;
`include "uvm_macros.svh"
class pkt_env extends uvm_env;
`uvm_component_utils(pkt_env)
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction
virtual function void connect_phase(uvm_phase phase);
`uvm_info(get_type_name(), "connect_phase() type name", UVM_LOW)
`uvm_info(get_full_name(), "connect_phase() full name", UVM_LOW)
$display({"full name: ", get_full_name()});
endfunction
endclass : pkt_env
module top;
pkt_env p1,p2;
initial begin
p1 = new("p1", null);
p1.connect_phase(null);
p2 = new("", null); // no name
p2.connect_phase(null);
end
endmodule : top