Why can't parameter class typedefs be used in variable declarations?

SystemVerilog
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7

In reply to dave_59:

I think I’m running the same example

// Test type operator

class env #(type P, type V);
  type(V::bus_loopback_vif_t) bus_loopback_direct_vif;
endclass

module top;
class B;
  typedef int bus_loopback_vif_t;
endclass
  env#(int, B) e;
endmodule

I get these messages

QuestaSim vlog 10.2a Compiler 2013.03 Mar 15 2013
– Compiling package test_sv_unit
** Error: test.sv(4): Type-reference expression may not have hierarchical refs. or elements of dynamic types.
– Compiling module top
** Error: test.sv(4): Type-reference expression may not have hierarchical refs. or elements of dynamic types.

Maybe it’s a compiler dependency?