Why base class can't be assigned to derived class?

SystemVerilog
, ,
5

Thanks Dave.

When derived class assigned to base class, hope same rule applicable, then why tool not issuing any error.

class A;
  bit var1;
endclass

class B;
  bit var1;
endclass

module top;
  A a =new();
  B b =new();
  initial
    a = b; // No Compilation error
endmodule