Why are some flops designed as non-resettable ? And those needs to be forced to some value during GLS sims?

SystemVerilog
1

Hello Folks,

a. Why do they design some flops with non-resettable characteristics ?
b. And in-order to make the GLS sims move forward, these flops are forced to some default values ?
c. What will happen to these flops in reality in silicon ?

It would be great if someone can share their comments/thoughts on the above questions !

Thanks,

2

Since not all registers need to be reset, it is more effective and eficient to design them without the reset logic. These regs include pipelined and loadable and need not the reset feature. .
Other designs are reset with set scan at initialization.
In Real silicon a reg will stabilize to 0 or 1 @ power-up.
Ben Ben@systemverilog.us

3

In reply to ben@SystemVerilog.us:

Hello Ben,

Thanks for your response. But just a small clarification, when you said “it is more effective and efficient to design them without the reset logic”, effective & efficient in what ways ? Can you kindly give some examples ?

Thanks !

4

In reply to desperadorocks:

It’s a matter of additional logic and routing per FF. Though small, it still takes real estate. Fewer gates generally imply higher speed.
The old TI books showed the logic of FF, like the 5474 TTL.
Maybe it’s on the web.
Ben Ben@systemverilog.us