When master signal is asserted a slave signal should be asserted after some time delay. the assertion is not failing if the duration is more

SystemVerilog
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3

In reply to ben@SystemVerilog.us:

In reply to srirahulch95:
Time should be in number of clock cycles, not in ns.


Let max_cycles=20;
ap_max: assert property(
@(posedge clk) $rose(master_rise) |-> ##[1:max_cycles] $rose(slave_rise));

Ben systemverilog.us

Looks like his intention is to check if the delay between slave_rise and master_rise is equal to the expected duration.

In that case he should use ##[0:] instead of [*0:].
Below code should serve the intention.

property p_max_time(clk,master_rise,slave_rise,duration);
time start_time;
@(posedge clk) ($rose(master_rise),start_time = $realtime) |-> ##[1:$] $rose(slave_rise) ##0 (($realtime -start_time) == duration);
endproperty

Regards,
Manju
https://www.linkedin.com/in/manjubhat/