When master signal is asserted a slave signal should be asserted after some time delay. the assertion is not failing if the duration is more

SystemVerilog
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2

In reply to srirahulch95:
Time should be in number of clock cycles, not in ns.


Let max_cycles=20;
ap_max: assert property(
@(posedge clk) $rose(master_rise) |-> ##[1:max_cycles] $rose(slave_rise));

Ben systemverilog.us