Waiting for clocks in sequence

UVM
,
1

Hi All,
This may seem to be a basic question.
But I need to know methodology and correct way of doing it.

If I have to wait for some clocks in sequence , how do we achieve it ?

  1. In driver , we have interface handle so there we can wait and use uvm_event ??
  2. Use #delays in sequence .

Thanks and Regards,
GG

2

Hi Gaurav,
You can use the same uvm_event which you have mentioned .
You can get the event with the help of uvm_event_pool, the sharing of the event happens with respect to the name with which you have set your clock event.
Please find the code snippet below.

example:


class my_sequence extends uvm_sequence;
//factory registration 
//other stuff

  uvm_event_pool my_event_pool;
  uvm_event clk_event;
  .
  .
  .
  clk_event = new();
  my_event_pool =  uvm_event_pool::get_global_pool();
  `uvm_info(get_full_name(),my_event_pool.get_type_name(),UVM_HIGH);
  
  task body();
      clk_event = my_event_pool.get("CLOCK EVENT");//this clock event will be triggered and set in the event pool with the same name in some other place where you have the access to the virtual interface handle.
      .
      .
      .
      clk_event.wait_trigger;
      .
      .
  endtask
endclass

I hope this helps in solving your problem.

Thanks,
Neith

3

In reply to UVM Beginner:

Thanks for the clear explanation.
Helps a lot.

Regards,
GG

4

Using a uvm_event_pool is not recommended as it results in an environment that is very co-dependent on other components and isn’t very portable.

Our recommendation it to create an agent which can be used for time/clock advancement. It would have an interface connected to a system clock and have a sequence which would complete when a specified number of clocks have passed.

This technique is recommended since it removes all timing from the HVL testbench and is portable to both simulation and emulation.

5

In reply to gaurav_7589:

You can get the virtual interface in your sequence and then wait for the number of clocks that you want. Make sure that the interface has a clock connected to the design clock.

6

In reply to jasmine_ti:

This is not a good decision. Becaus the sequencer is not an active component. The sequencer is controlled by the driver. Always when you are calling get/get_next_item the next seq_item will be generated. Make your timimg in the driver. You have the clock here.

7

In reply to chr_sue:

Yes, The suggestion provided by @chr_sue will more recommended, but if you do not have control over it, you can use put_response and get_response method in driver and sequence. which will hold your sequence to be randomize and send the next packet.

8

In reply to jasmine_ti:

You can put in an interface handle, but it will not have so much influence. The sequencer cannot initiate an action. This will be done by the driver. This is not a question of recommendation or not.