Using a uvm_event_pool is not recommended as it results in an environment that is very co-dependent on other components and isn’t very portable.
Our recommendation it to create an agent which can be used for time/clock advancement. It would have an interface connected to a system clock and have a sequence which would complete when a specified number of clocks have passed.
This technique is recommended since it removes all timing from the HVL testbench and is portable to both simulation and emulation.