Verification of ASYNCHRONOUS FIFO

UVM
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In reply to ben@SystemVerilog.us:

Hi Ben,

Apologize for re-opening this thread after 2 years. I’m just now becoming active on forums.

In my view, 2-agents would be a better choice(Please correct, if not)

  • Independent WRITE and READ agents sequences of which can be coordinated in the virtual sequence.

  • Monitors of both the agents shall feed the Scoreboard.

  • Scoreboard will have a FIFO which itself is the high level model of the DUT.

  • Scoreboard (being an uvm_component) in addition to data integrity check shall also generate FULL and EMPTY events using the FIFO size. These events (on SV interface) in turn shall be used to implement SVA.

Please help me understand if we miss anything BIG with such architecture.

Thanks,
Prem