Variable range in system verilog assertion property

[MadhukarN]

Hi All,

I am trying to check the req and ack timing. Where the range needs to be varied.

property req_ack_timing;
@(posedge clk)
$rose(req) |-> ##[0:num_clks] $rose(ack);
endproperty : req_ack_timing

Here, the num_clks changes during the run time. While compiling this, I get non-constant expression used.
Is there a way to check an assertion of a signal in a range which can change during run time?

Thanks,
Madhukar

[dave_59]

In reply to MadhukarN:

You need to create a local down counter:

https://verificationacademy.com/forums/systemverilog/assertion-check-signal-value-between-min-and-max-range#reply-60714

Since you are starting at 0, you could probably simplify it.

[ben2]

In reply to dave_59:
I just posted this package:
****SVA: Package for dynamic and range delays and repeats [/b]
https://verificationacademy.com/forums/systemverilog/sva-package-dynamic-and-range-delays-and-repeats

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

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