Assertion to check signal value between MIN and MAX range

Hi All,

I have written below assertion to check signal B value within given range.

property p_delay_equivalent();
@(posedge clk) disable iff(0)
$rose(a) |-> ##[1:5] (b == 1);
endproperty

a2_delay_equivalent: assert property(p_delay_equivalent)
else $display(“FAILED”);
Above code is working fine, but I want to used variable instead of fixed value but SVA is not allowing to used it.

For example ,

$rose(a) |-> ##[min:max] (b == 1); //Error

Anyone suggest how to write an assertion to cover above scenario with random range.??

In reply to pvpatel:
The following is a variation of a model in my SVA Handbook 4th Edition, 2016 Code is also at http://SystemVerilog.us/vf/minmax2.sv


// $rose(a) |-> ##[min:max] (b == 1); //Error 
import uvm_pkg::*; `include "uvm_macros.svh" 
module top; 
	bit clk, a, b;  
	int min=2, max=7, thread; 
	default clocking @(posedge clk); endclocking
	initial forever #10 clk=!clk;  
	
	
	// ap_range_fix: assert property($rose(a) |-> ##[min:max] b);
	property p_range_equivalent; // Equivalent implementation
	  int vmin, vmax, vdelta; // this is an internal local variable defined by the tool
	  ($rose(a), vmin=min, vdelta=max-min) |-> 
	     first_match((1, vmin=vmin-1'b1)  [*0:$] ##1 vmin<=0)// wait for min cycles 
	 ##0 first_match((1, vdelta=vdelta -1)[*0:$] ##1 (b || vdelta<=0))
	 ##0 b; // test for b in case above finished because vdelta <=0
	endproperty
	ap_range_equivalent: assert property(p_range_equivalent);
	
		
	initial begin 
		repeat(100) begin 
			@(posedge clk);   
			#2 if (!randomize(a, b)  with 
					{ a dist {1'b1:=1, 1'b0:=6};
					  b dist {1'b1:=1, 1'b0:=11};
					}) `uvm_error("MYERR", "This is a randomize error")
		end 
		repeat(100) begin 
		@(posedge clk);   
			#2 if (!randomize(a, b)  with 
						{ a dist {1'b1:=1, 1'b0:=6};
							b dist {1'b1:=1, 1'b0:=1};
						}) `uvm_error("MYERR", "This is a randomize error")
		end 	    		
		
		$stop; 
	end 
endmodule  

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact http://cvcblr.com/home


In reply to ben@SystemVerilog.us:
This assertion can also be more easily written answered through the use of an automatic task.
I discuss this approach in my paper:
https://verificationacademy.com/forums/systemverilog/paper-understanding-sva-engine-simple-alternate-solutions
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr