a2_delay_equivalent: assert property(p_delay_equivalent)
else $display(“FAILED”);
Above code is working fine, but I want to used variable instead of fixed value but SVA is not allowing to used it.
For example ,
$rose(a) |-> ##[min:max] (b == 1); //Error
Anyone suggest how to write an assertion to cover above scenario with random range.??
// $rose(a) |-> ##[min:max] (b == 1); //Error
import uvm_pkg::*; `include "uvm_macros.svh"
module top;
bit clk, a, b;
int min=2, max=7, thread;
default clocking @(posedge clk); endclocking
initial forever #10 clk=!clk;
// ap_range_fix: assert property($rose(a) |-> ##[min:max] b);
property p_range_equivalent; // Equivalent implementation
int vmin, vmax, vdelta; // this is an internal local variable defined by the tool
($rose(a), vmin=min, vdelta=max-min) |->
first_match((1, vmin=vmin-1'b1) [*0:$] ##1 vmin<=0)// wait for min cycles
##0 first_match((1, vdelta=vdelta -1)[*0:$] ##1 (b || vdelta<=0))
##0 b; // test for b in case above finished because vdelta <=0
endproperty
ap_range_equivalent: assert property(p_range_equivalent);
initial begin
repeat(100) begin
@(posedge clk);
#2 if (!randomize(a, b) with
{ a dist {1'b1:=1, 1'b0:=6};
b dist {1'b1:=1, 1'b0:=11};
}) `uvm_error("MYERR", "This is a randomize error")
end
repeat(100) begin
@(posedge clk);
#2 if (!randomize(a, b) with
{ a dist {1'b1:=1, 1'b0:=6};
b dist {1'b1:=1, 1'b0:=1};
}) `uvm_error("MYERR", "This is a randomize error")
end
$stop;
end
endmodule