Variable Delay for SystemVerilog Assertion

SystemVerilog
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1

Hello.

It seems that I can’t use variables in delays and repetitions for SystemVerilog assertion.
(Please let me know if there had been any change in specification on this.)

Below two examples are the ones that I would like to implement in SVA.
But since the delays and repetitions are not constant, the simulator flags an error.

Case 1: (expr)[*(variable)]


// t1: parameter, r: integer
property p_test;
    @(negedge clk) disable iff (!rstn)
    $rose(cs) |-> (!cs)[*(t1 * r):$] ##1 $rose(cs);
endproperty
endmodule: test

Case 2: ##[variable]


// t2: parameter, r: integer
property p_test;
    @(negedge clk) disable iff (!rstn)
    $rose(cs) |-> ##[(t2 * r):$] $rose(capture);
endproperty
endmodule: test

I’ve found following two articles but I don’t think I’m getting it yet…
https://verificationacademy.com/forums/systemverilog/use-non-constant-expression-property-assertion
https://verificationacademy.com/forums/systemverilog/range-issue-systemverilog-property

Thank you.

2

Read my paper.

Abstract: Understanding the engine behind SVA provides not only a better appreciation and limitations of SVA, but in some situations provide features that cannot be simply implemented with the current definition of SVA. This paper first explains, by example, how a relatively simple assertion example can be written without SVA with the use of SystemVerilog tasks; this provides the basis for understanding the concepts of multithreading and exit of threads upon a condition, such as an error in the assertion. The paper then provides examples that uses computational variables within threads; those variables can cause, in some cases, errors in SVA. The strictly emulation model with tasks solves this issue.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

  • SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
3

In reply to ben@SystemVerilog.us:

Thanks, Ben.
Examples of using variables in property and the SVA using tasks helped.