To use "NON-CONSTANT EXPRESSION" in property for assertion

SystemVerilog
1 
assign DCR_CLK = testbench.sw_top_inst.DUT.megatron_x.megatron_cib.dcr_slave_cfg.DCR_clk;
 assign DCR_TIMEOUT_WAIT = testbench.sw_top_inst.DUT.megatron_x.megatron_cib.dcr_slave_cfg.dcr_timeout_wait[15:0];
 assign SLV_DCR_TIMEOUT_WAIT = testbench.sw_top_inst.DUT.megatron_x.megatron_cib.dcr_slave_cfg.Sl_dcrTimeoutWait;
 assign SCRUB_INIT = testbench.sw_top_inst.DUT.megatron_x.megatron_cib.dcr_slave_cfg.scrub_init;
// end 
 //=================ASSERTION TO CHECK SLV_DCR_TIMEOUT_WAIT============================//
 property slv_dcr_timeout_wait;
   @(posedge DCR_CLK)
       disable iff (!DCR_TIMEOUT_WAIT)
         $rose(SCRUB_INIT) |-> $rose(SLV_DCR_TIMEOUT_WAIT) ##(DCR_TIMEOUT_WAIT) $fell(SLV_DCR_TIMEOUT_WAIT);
 endproperty : slv_dcr_timeout_wait
 
 assert property (slv_dcr_timeout_wait);

hi ,
here SLV_DCR_TIMEOUT_WAIT is the value programmed in the register hence it is not a constant value, how can i use the same in assertion.

error is :
Error-[SVA-INCE] Illegal use of non-constant expression
/lsi/designs/rsd_megatron/team/singhs/megatron/sim/testbench/mss_tb/interfaces/mss_internal_signal_if.sv, 41
mss_internal_signal_if, “DCR_TIMEOUT_WAIT”
The use of a non-constant expression is not allowed in properties, sequences
and assertions for cases such as delay and repetition ranges.
Please replace the offending expression by an elaboration-time constant.

2

See range issue in systemverilog property | Verification Academy

3 
Below are equivalent assertions:
// a |=> ##v b) // v is a module variable 
property p_delay_equivalent; // Am producing an equivalent implementation
  int local_v; // this is an internal local variable defined by the tool
  a |=> (1, local_v = v)
         ##0 (1, local_v=local_v - 1'b1)[*0:$]
         ##1 local_v<0
         ##0 b;
endproperty
ap_delay_equivalent: assert property(@(posedge clk)ap_delay_equivalent);

// a |=> ##[0:v] ##1 b)
property p_range_equivalent; // Am producing an equivalent implementation
   int local_v; // this is an internal local variable defined by the tool
   a |=> (1, local_v = v)
         ##0 (local_v<0, local_v=local_v - 1'b1)[*0:$] ##1 b;
endproperty
ap_range_equivalent: assert property(@(posedge clk)ap_range_equivalent);

BTW, you’ll be able to use variables in delays and repeat operators in the next release of 1800 (maybe by end of 2015 or early 2016; that is in the plans.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

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4

In reply to dave_59:

hi dave ,
i went thro the same and modified my assertion accordingly:

 //=================ASSERTION TO CHECK SLV_DCR_TIMEOUT_WAIT============================//
 property slv_dcr_timeout_wait_p;
   int v;
   @(posedge DCR_CLK)
       disable iff (!DCR_TIMEOUT_WAIT)
         $rose(SCRUB_INIT) |-> $rose(SLV_DCR_TIMEOUT_WAIT) ##3 $fell(SLV_DCR_TIMEOUT_WAIT);
          endproperty : slv_dcr_timeout_wait_p
 
 slv_dcr_timeout_wait_a: assert property (slv_dcr_timeout_wait_p) $info("assertion is trigerred"); else $error("assertion failed at time %0t",$time);
 //=================ASSERTION TO CHECK SLV_DCR_TIMEOUT_WAIT============================//
 

  //=================ASSERTION TO CHECK SLV_DCR_TIMEOUT_WAIT============================//
  property slv_dcr_timeout_wait_p_1;
   int v;
   @(posedge DCR_CLK)
       disable iff (!DCR_TIMEOUT_WAIT)
         $rose(SCRUB_INIT) |-> ($rose(SLV_DCR_TIMEOUT_WAIT), v=DCR_TIMEOUT_WAIT+1'b1) |->  (1, v=v-1'b1)[*0:$] ##1 v==0 ##0 $fell(SLV_DCR_TIMEOUT_WAIT);
 endproperty : slv_dcr_timeout_wait_p_1
 
 slv_dcr_timeout_wait_a_1: assert property (slv_dcr_timeout_wait_p_1) $info("assertion_1 is trigerred"); else $error("assertion_1 failed at time %0t",$time);
 //=================ASSERTION TO CHECK SLV_DCR_TIMEOUT_WAIT============================//

but the second assertion is not getting trigerred, can you please let me know what mistake i am commiting here.
value of DCR_TIMEOUT_WAIT = 3