Vacuous pass in SV Assertion

SystemVerilog
, ,
1

Hi All,

I just saw the assertion control task called $assertvacuousoff to turn off the pass action block in case of any false pass. I dont know how to use it in my assertion property. For example I have the following property:

property ex;
@(posedge clk) $rose(a) |-> $rose(b);
endproperty

assert property (ex) else $error();

Where do I write this task to check vacuous pass?

2

In reply to atanubiswas:

turn off the pass action block in case of any false pass

There no such thing as a “false pass”; it is called a vacuous successe or a vacuuss pass.
To use those action control tasks, insert them in a block, such as the initial or always block.
Thus, your assertion will look like the following:


  // For straightforward, not reused assertions with no local variables, avoid declaring 
  // property first, it is no needed. 
  initial $assertvacuousoff(0);
    // initial $assertpassoff(0);
  pa_ab: assert property(@ (posedge clk) $rose(a) |-> b)
        $display ("@ %t PASS:  a=%b b=%b", $realtime, $sampled(a), $sampled(a));
        else $display ("@ %t FAIL:  a=%b b=%b", $realtime, $sampled(a), $sampled(a));

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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    https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment
3

Loading snapshot worklib.t:sv … Done
initial $assertvacuousoff();
|
xmsim: *E,MSSYSTF (…/design/clk_check.sv,15|24): User Defined system task or function ($assertvacuousoff) registered during elaboration and used within the simulation has not been registered during simulation.
TOOL: xrun 23.05-a071: Exiting on Sep 02, 2024 at 11:30:12 PDT (total: 00:00:13)
getting this error , can anyone help.

4
1 Like
5

Hi @dave_59 , i have gone through SV LRM, page 611

Similarly, assertion action control tasks $assertpasson, $assertpassoff, $assertfailon,
$assertfailoff, $assertvacuousoff, and $assertnonvacuouson are provided for convenience and
backward compatibility. These tasks can be defined as follows:
— $assertpasson[(levels[, list])] is equivalent to $assertcontrol(6, 31, 7, levels [,list])
— $assertpassoff[(levels[, list])] is equivalent to $assertcontrol(7, 31, 7, levels [,list])
— $assertfailon[(levels[, list])] is equivalent to $assertcontrol(8, 31, 7, levels [,list])
— $assertfailoff[(levels[, list])] is equivalent to $assertcontrol(9, 31, 7, levels [,list])
— $assertnonvacuouson[(levels[, list])] is equivalent to $assertcontrol(10, 31, 7, levels [,list])
— $assertvacuousoff[(levels[, list])] is equivalent to $assertcontrol(11, 31, 7, levels [,list])

so i think its not compatible in newer compiler.

so i tried with the equivalent sytem task → $assercontrol () with cadence compiler

initial $assertcontrol(11,1);
                     |
xmsim: *W,ILUNIP (../design/clk_check.sv,15|21): Illegal or no value provided as second argument of $assertcontrol task. Assuming unique, unique0 and priority.
initial $assertcontrol(11,1);
                     |
xmsim: *W,ILUNPR (../design/clk_check.sv,15|21): Illegal value provided as first argument of $assertcontrol task. Assuming value 3.
Simulation complete via $finish(1) at time 40 NS + 0
../design/clk_check.sv:12 $finish();
xcelium> exit
TOOL:	xrun	23.05-a071: Exiting on Sep 02, 2024 at 22:39:48 PDT  (total: 00:00:17)