Turn off vacuous success in SystemVerilog assertions

The syntax is: $assertvacuousoff [(levels[, list])]
I is equivalent to $assertcontrol(11, 31, 7, levels [,list])

$assertpassoff (0, top_tb.cpu_rtl_1); // Disabling all assertions action blocks on passes
$assertvacuousoff(0); // Disable pass action block for vacuous successes
I recommend using the $assertvacuousoff(0) because the pass action block for vacuous successes is typically not useful.

[1] The levels indicate the level of the hierarchy below each specified module. This level is consistent with the corresponding argument to the $dumpvars system task (see 1800-2012 section 21.7.1.2).

Setting the first argument to 0 causes a dump of all variables in the specified module and in all module instances below the specified module. The argument 0 applies only to subsequent arguments that specify module instances, and not to individual variables.
Example 1: $dumpvars (1, top);
Because the first argument is a 1, this invocation dumps all variables within the module top; it does not dump variables in any of the modules instantiated by module top.


Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • SystemVerilog Assertions Handbook 3rd Edition, 2013 ISBN 878-0-9705394-3-6
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115