I am trying to jump some of the phases in my TB in order to skip certain unnecessary checks and save some time. But I see some discrepancies.
There are two environments and two separate domains assigned to them as shown below. When domain1 is in shutdown phase, domain2 enters in main phase, this suggests that both the domains run independently of each other (as expected).
// Displays are there in every phase of environment
class test extends uvm_test;
`uvm_component_utils(test)
function new (string name, uvm_component parent);
super.new(name, parent);
endfunction
env m_env1;
env m_env2;
uvm_domain domain1;
uvm_domain domain2;
function void build_phase(uvm_phase phase);
// This part domain1 and domain2 are running independently
// uvm_config_db#(int)::set(this, "m_env1", "delay", 10);
// Use different delays to see that domain1 and domain2 run independently
uvm_config_db#(int)::set(this, "m_env1", "delay", 100);
uvm_config_db#(int)::set(this, "m_env2", "delay", 100);
m_env1 = env::type_id::create("m_env1", this);
m_env2 = env::type_id::create("m_env2", this);
domain1 = new("domain1");
m_env1.set_domain(domain1);
domain2 = new("domain2");
m_env2.set_domain(domain2);
//domain1.sync(domain2);
endfunction
function void start_of_simulation_phase(uvm_phase phase);
this.set_report_verbosity_level_hier(UVM_FULL);
endfunction
task run_phase(uvm_phase phase);
#250;
`ifdef EXTRACT_PH_JUMP // USE THIS SWITCH TO JUMP TO EXTRACT PHASE
// Both domain1 and domain2 jumps to extract phase unexpectedly.
// this is for domain2 to jump to extract phase
domain2.jump(uvm_extract_phase::get());
`else
// Both domain1 and domain2 jumps to repective phases other than extract phase. I would expect only domain2 to jump and wait and domain1 to continue phase execution.
// domain2 should wait till domain1 completes other phases
// this is for domain2 to jump to final phase
domain2.jump(uvm_final_phase::get());
`endif
endtask
endclass
// Output when jumping to extract phase. Extract phase display comes twice.
UVM_INFO /apps/vcsmx/etc/uvm-1.2/src/base/uvm_phase.svh(1552) @ 250: reporter [PH_JUMP] phase main (schedule uvm_sched, domain domain2) is jumping to phase extract
UVM_WARNING @ 250: main_objection [OBJTN_CLEAR] Object 'uvm_top' cleared objection counts for main_objection
UVM_INFO testbench.sv(78) @ 1040: uvm_test_top.m_env1 [uvm_test_top.m_env1] this is extract phase
UVM_INFO testbench.sv(78) @ 1040: uvm_test_top.m_env2 [uvm_test_top.m_env2] this is extract phase
UVM_INFO testbench.sv(78) @ 1040: uvm_test_top.m_env1 [uvm_test_top.m_env1] this is extract phase
UVM_INFO testbench.sv(78) @ 1040: uvm_test_top.m_env2 [uvm_test_top.m_env2] this is extract phase
When I jump from run phase to any phase, both the domain1 and domain2 skips the remaining phases and jumps to the intended phase. I would expect domain2 only to skip the phases and jump forward and wait (domain1 jumps unexpectedly). Is there any way to skip phases for domain2 only?
But when a jump happens from “run_phase” (or any other task phase) to “extract_phase”, then the “extract_phase” is getting called twice. This is certainly not expected. Is there any workaround for this?
Please provide some inputs regarding the two issues. Let me know where my understanding is lagging.
EDIT: MODIFIED THE CODE. USE “+define+EXTRACT_PH_JUMP” TO JUMP TO EXTRACT PHASE AND SEE THAT IT IS GETTING CALLED TWICE (SCENARIO-2). IF YOU DON’T USE THIS MACRO, THEN IT WILL JUMP TO FINAL PHASE (SCENARIO-1).
UVM_INFO testbench.sv(20) @ 0: uvm_test_top.m_env2 reset_phase called
UVM_INFO testbench.sv(20) @ 0: uvm_test_top.m_env1 reset_phase called
UVM_INFO testbench.sv(28) @ 100: uvm_test_top.m_env1 configure_phase called
UVM_INFO testbench.sv(28) @ 100: uvm_test_top.m_env2 configure_phase called
UVM_INFO testbench.sv(38) @ 200: uvm_test_top.m_env2 main_phase called
UVM_INFO testbench.sv(38) @ 200: uvm_test_top.m_env1 main_phase called
UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1314) @ 250: reporter [PH_JUMP] phase main (schedule uvm_sched, domain domain2) is jumping to phase final
Pardon for the confusion. I have updated the code in my question. Refer to the comments in build and run phase of test. Uncommented the code as required.
// ***** in build phase
// Uncomment this to see that domain1 and domain2 are running independently
// uvm_config_db#(int)::set(this, "m_env1", "delay", 10);
// Uncomment this to see that domain1 also jumps when domain2 jumps to final phase
uvm_config_db#(int)::set(this, "m_env1", "delay", 100);
uvm_config_db#(int)::set(this, "m_env2", "delay", 100);
// ***** in run phase;
// Both domain1 and domain2 jumps to extract phase unexpectedly.
// Uncomment this for domain2 to jump to extract phase
domain2.jump(uvm_extract_phase::get());
// Both domain1 and domain2 jumps to repective phases other than extract phase. I would expect only domain2 to jump and wait and domain1 to continue phase execution.
// domain2 should wait till domain1 completes other phases
// Uncomment this for domain2 to jump to final phase
//domain2.jump(uvm_final_phase::get());
I have tried with all simulators at EDAPlayground and got the same results. I believe that this should be independent of simulator.
It would help greatly if you would put `ifdefs around the code instead of trying to have different sets of code to comment or uncomment.
Then you can tell us to run the code with this +define+ switch and say you get “this set of results” when in fact you were expecting “that set of results”
Done. Please review the updated question and code.
EDIT: MODIFIED THE CODE. USE “+define+EXTRACT_PH_JUMP” TO JUMP TO EXTRACT PHASE AND SEE THAT IT IS GETTING CALLED TWICE (SCENARIO-2). IF YOU DON’T USE THIS MACRO, THEN IT WILL JUMP TO FINAL PHASE (SCENARIO-1).
Use appropriate macro to jump to extract phase or any other phase.
I’m not sure what the value of this example is. I recommend my customers always to decide what they are doing, going simply with the run_phase or using the sub-phases like reset_phase etc.
You should not mix them in 1 testbench.
The issue persists even if we jump from any of the sub-phases to extract phase.
This is a sample code. In the real testbench, it can be used to skip multiple phases and save the run time of simulation. It can be useful for some sanity type of tests where we don’t want thorough RTL checks.
What I mean is, if you are replacing in the test the run_phase by main_phase the jumping never happens. It happens only if you use the run_phase. I believe it is not a good coding style the employ both Kinds of phasing in a testbench, using in the env the run sub-phases and in the test run_phase.
I’m not sure if you are really saving time jumping from one phase to another. Only the run_phase and the sub-phases are consuming time. All the other phases are functions.
My experience shows the real delay comes always out of the RTL.
What I mean is, if you are replacing in the test the run_phase by main_phase the jumping never happens. It happens only if you use the run_phase.
Thanks for the inputs. I didn’t knew this. Is it documented somewhere? Can you please point me to some link where I can improvise my knowledge over this.
I tried using the run_phase everywhere in the current code. Then also the same issue of extract phase getting called twice, persists. Now I am using run_phase in environment and test both and jumping to extract_phase. Still I am seeing that extract phase is called twice. Moreover, there is no objection dropping when jump is called.
I have updated the code with “+define+USE_RUN_PH” switch. Refer to the same link for regenerating the issue. (Phase jumping - EDA Playground)
P.S.: I agree that the delay comes from the RTL, but still phase jumping will help in eliminating checks for several thousands of CSR-arrays in my case (these checks are in different components in top level TB).