In reply to sharvil111:
I guess you are simulating with VCS, right?
Using Questa I see a different result:
UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(215) @ 0: reporter [Questa UVM] QUESTA_UVM-1.2.2
UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(217) @ 0: reporter [Questa UVM] questa_uvm::init(+struct)
UVM_INFO @ 0: reporter [RNTST] Running test test…
UVM_INFO testbench.sv(20) @ 0: uvm_test_top.m_env2 reset_phase called
UVM_INFO testbench.sv(20) @ 0: uvm_test_top.m_env1 reset_phase called
UVM_INFO testbench.sv(28) @ 100: uvm_test_top.m_env1 configure_phase called
UVM_INFO testbench.sv(28) @ 100: uvm_test_top.m_env2 configure_phase called
UVM_INFO testbench.sv(38) @ 200: uvm_test_top.m_env2 main_phase called
UVM_INFO testbench.sv(38) @ 200: uvm_test_top.m_env1 main_phase called
UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1314) @ 250: reporter [PH_JUMP] phase main (schedule uvm_sched, domain domain2) is jumping to phase final
UVM_WARNING @ 250: main_objection [OBJTN_CLEAR] Object ‘uvm_top’ cleared objection counts for main_objection
UVM_INFO testbench.sv(66) @ 250: uvm_test_top.m_env1 [uvm_test_top.m_env1] this is final phase
UVM_INFO testbench.sv(66) @ 250: uvm_test_top.m_env2 [uvm_test_top.m_env2] this is final phase
It does not jump th the extract phase.