Uvm_event

UVM
1

Hi,

I have two drivers drv1 and drv2. I want to drive mod1 and mod2. There are few signals connected between module1 and module2 and remaining signals are connected directly to the ports. So i want to drive the signals to module2 after the signals from module1 are available. how to synchronize the signals from module1 and signals that are connected directly to the ports.

Thanks,
Ashok

2

In reply to ashokgupta466:

Your driver drv2 should have access to all signals that are inputs to mod2 - hence it can wait for them as needed. What’s not working, if any?

Srini
www.verifwoks.com

3

In reply to Srini @ CVCblr.com:

Hi srini

I have access to all signals that are inputs to module 2, but how to synchronize between the signals that are applied directly and the signals coming from module 1.

Thanks

4

In reply to ashokgupta466:

What do you mean with ‘applied directly’? All input signals should be driven from any UVM driver. Do you have dependencies between your functtional interfaces?

5

In reply to chr_sue:

Every input is driven from UVM driver. I have a DUT which is having 3 sub modules mod1,mod2,mod3. For these DUT i’m trying to construct a TB, by using these TB i should be able to verify individually each module or sub system (ex. mod1+mod2). For each module i am having separate interfaces and agents. so here i want to verify subsystem (mod1+mod2), there are some signals going from mod1 to mod2. FOr mod2 the input signals should be driven from driver after the intermediate signals from mod1 are available. How to synchronize the intermediate signals from mod1 and signals that are driven from driver.

6

In reply to ashokgupta466:

There is a conflict in your description. On the one side you are saying all input signals are driven from the corresponding driver. On the other hand you are saying you have to wait for some signals from another sub-module.
Are you sure your interface definitions are useful?

7

In reply to chr_sue:

Hi Ashok,

The signals which are part of the mod1+mod2 interface, are they being driven by both the interfaces ?

module top;

abc a1(.clk(vif1.clk1),.reset(vif1.reset1),.enable_1(vif1.enable_1));

def d1(.clk(vif2.clk2),.reset(vif2.reset2), .enable_1(vif2.enable_1),.enable_2(vif2.enable_2));

endmodule

Interface vif1;
logic clk1;
logic enable_1;
logic reset1;
endinterface

Interface vif2;
logic clk2;
logic reset2;
logic enable_1;
logic enable_2;
endinterface

So, as the example goes, is it true that “enable_1” is being driven from both the interface vif2 for module “def” and also by module “abc” ?

I’ve a crude soln. for this issue. in the driver of the “def” module, which’ll have the handle for vif2, its good to poll for “vif2.enable_1” and if it hasn’t toggled/not driven by mod1, i.e. if it is in a position where it can be driven by vif2, only then drive it.

I’m sure there are better solutions. I’m also looking fwd to know about it.

8

In reply to sri205:

If you do not know which relationship and functionality is behind the enable1/2 it is impossible to advice with a good solution.
Please explain.

9

In reply to chr_sue:

A simple example will be a shared area such as banks of DRAM with processor and a DMA with an enable for bank. At the end of the day, its just shared resource, isn’t it ?

But I believe I’m wrong in my particular understanding. If I’m not mistaken, the question is about how two modules of an env can be checked together.

In such a scenario, its possible that timing between the two modules might also play a role. I’m also looking to find a particular soln. like this, which i’ll post as a separate thread.

10

In reply to sri205:
Hi sri205,

yes, the signals that are part of the mod1+mod2 interface, are being driven by both the interfaces.

And facing a problem similar to this “enable_1” is being driven from both the interface vif2 for module “def” and also by module “abc”

can you elaborate the solution.

Thanks Ashok

11

In reply to ashokgupta466:

It seems you need really the uvm_event. Please visit page 261 of the UVM Cookbook (Alternative Implementation Pattern Using Events To Signal Completion) to find an example for uvm_event.

12

In reply to chr_sue:

@ashok

I think if you follow chr_sue’s suggestion, it’d be better. Here is a good link

uvm_events

Thanks chr_sue