In reply to chr_sue:
Every input is driven from UVM driver. I have a DUT which is having 3 sub modules mod1,mod2,mod3. For these DUT i’m trying to construct a TB, by using these TB i should be able to verify individually each module or sub system (ex. mod1+mod2). For each module i am having separate interfaces and agents. so here i want to verify subsystem (mod1+mod2), there are some signals going from mod1 to mod2. FOr mod2 the input signals should be driven from driver after the intermediate signals from mod1 are available. How to synchronize the intermediate signals from mod1 and signals that are driven from driver.