In reply to chr_sue:
Hi Ashok,
The signals which are part of the mod1+mod2 interface, are they being driven by both the interfaces ?
module top;
abc a1(.clk(vif1.clk1),.reset(vif1.reset1),.enable_1(vif1.enable_1));
def d1(.clk(vif2.clk2),.reset(vif2.reset2), .enable_1(vif2.enable_1),.enable_2(vif2.enable_2));
endmodule
Interface vif1;
logic clk1;
logic enable_1;
logic reset1;
endinterface
Interface vif2;
logic clk2;
logic reset2;
logic enable_1;
logic enable_2;
endinterface
So, as the example goes, is it true that “enable_1” is being driven from both the interface vif2 for module “def” and also by module “abc” ?
I’ve a crude soln. for this issue. in the driver of the “def” module, which’ll have the handle for vif2, its good to poll for “vif2.enable_1” and if it hasn’t toggled/not driven by mod1, i.e. if it is in a position where it can be driven by vif2, only then drive it.
I’m sure there are better solutions. I’m also looking fwd to know about it.