UVM Constraint Randomization does not work as expected

UVM
,
1

I have a UVM test that calls a test sequence and randomizes it as follows,

class rd_test extends base_test;
`uvm_component_utils(rd_test)

q_pkg::q_vseq rd_seq;

virtual task main_phase(uvm_phase phase);
q_pkg::q_vseq rd_seq;
phase.raise_objection(this, “RD_TEST”);
rd_seq = q_pkg::q_vseq::type_id::create(“rd_seq”);
assert(rd_seq.randomize());
rd_seq.start(env.vsqr);
#10us;
if(!rd_seq.randomize() with {
0 < q_id < 8;
})
`uvm_fatal(get_type_name(), “Randomization failed”)
else
rd_seq.start(env.vsqr);
phase.drop_objection(this, “RD_TEST”);
endtask : main_phase

endclass : rd_test

class q_vseq extends vseq;

rand int q_id;

uvm_object_utils_begin(q_pkg::q_vseq) uvm_field_int(q_id, UVM_ALL_ON);
`uvm_object_utils_end

constraint q_id_c {0 < q_id < 8};

endclass : q_vseq

The problem is, I do not see q_id getting constraint between 0 to 8 using both constraints inside the sequence and inline sequence as in the test, unless I call the randomization call as follows
assert(rd_seq.randomize() with {q_id==7;});

Can someone help understand what’s missing?

2

This expression does not do what you think it does:


0 < q_id < 8

If you want the variable to be greater than 0 and less than 8, one way to do it is to use 2 expressions. Here is a complete example:

class q_vseq;
    rand int q_id;
    constraint q_id_c {
        0 < q_id;
        q_id < 8;
    }
endclass : q_vseq

module tb;

q_vseq q;

initial begin
    q = new();
    repeat (5) begin
        if (!q.randomize()) $display("fail");
        $display(q.q_id);
    end
end
endmodule

Here is another way:


    constraint q_id_c { q_id inside {[1:7]}; }
3

In reply to cool_toad:

See https://verificationacademy.com/forums/systemverilog/constraints-1#reply-56788