In Systemverilog why multiple relational operators are not allow in the constraint block ?
class Bus
rand bit[15:0] a,b,c;
constraint c1 { 0 < a < b < c; }
endclass
*In reply to Hardik Trivedi:*You can certainly put as many relational operators as you want in a constraint block - it just does not give you the results you are looking for. A constraint expression evaluates true or false following the same Boolean/arithmetic rules found elsewhere in SystemVerilog (like the condition of an if statement)… Those rules (from table 11-2) say that the operators associate from left to right. So your constraint expression evaluates the same as
{( (0 < a) < b) < c;}
Since the result of a single relational operator is a single bit, you don’t get what you expect.
What you really want is this expression
{0 < a && a < b && b < c;}
But since all constraint must evaluate true, you can write this as three separate constraint and save a few keystrokes.
{0 < a ; a < b ; b < c;}