Unpacked array concatenation assignment

SystemVerilog
, ,
1

Good Morning !

I’m failing to do a simple concatenation assignment to an unpacked array:


parameter int c_data_width = 16;
var logic [c_data_width-1:0] a;
var logic [c_data_width-1:0] a_z [2:0];

so if i do this, it works


a_z[0]   <= a;
a_z[1]   <= a_z[0];
a_z[2]   <= a_z[1];

but i want to write it something like this


a_z   <= {a_z[1:0],a};

Of couse this gives an error in Questasim-64 10.5b.

I ask for some guidance.
Thank you for the help you can provide !

Best regards,

StefanieCG

2

In reply to stefaniecg:

Try ’ (tick) for unpacked assignment,

a_z <= '{a_z[1:0], a};
3

In reply to MayurKubavat:

Thank you for your comment, nevertheless i get The same error as before:

“Illegal assignment to type ‘reg[c_data_width-1:0] $[2:0]’ from type ‘concat’: LHS and RHS types do not match.”

4

In reply to stefaniecg:

Hi,

I’ve checked syntax you are using. It works fine for other tools, your questa version is not supporting the syntax!

//This works fine. Although using tick
//gives error saying "expected arguments (3) but 
//provided arguments (2) only"
a_z <= {a_z[1:0],a};

Checkout same snippet on www.edaplayground.com and see if its supported by other tools as well.

5

In reply to MayurKubavat:

@MayurKubavat, Thank you for the feedback !

6

In reply to stefaniecg:

This worked for me in Questa

module top;
   parameter int c_data_width = 16;
   var logic [c_data_width-1:0] a;
   var logic [c_data_width-1:0] a_z [2:0];

   initial a_z   <= {a_z[1:0],a};

endmodule

So there must be something else wrong you are not showing.
Putting the ’ infront making it become an assignment pattern is wrong, you need 3 items in the pattern.

7

In reply to dave_59:

@Dave, Morning !

Thank for your feedback. Indeed there is more to it.
I didn’t thought the context matter, but it does.
The following code does give the error that I’m having, in the context in which i’m having it.


module top;
  parameter int c_data_width = 16;
  var logic [c_data_width-1:0] ramp_data = 0;
  var logic clk_top = 0;
  
  always #(10ns) clk_top = ~clk_top;
  always @(negedge clk_top) ramp_data = ramp_data + 1;
  
  checker top_checker (input logic clk, input logic [c_data_width-1:0] a);
    var logic [c_data_width-1:0] a_z [2:0];
    always_ff @(posedge clk) begin
      a_z <= {a_z[1:0], a};
    end
  endchecker
  
  top_checker i_top_checker(.clk(clk_top), .a(ramp_data));
endmodule

Thank you for the help you can provide