Unpacked array concatenation assignment

SystemVerilog
, ,
6

In reply to stefaniecg:

This worked for me in Questa

module top;
   parameter int c_data_width = 16;
   var logic [c_data_width-1:0] a;
   var logic [c_data_width-1:0] a_z [2:0];

   initial a_z   <= {a_z[1:0],a};

endmodule

So there must be something else wrong you are not showing.
Putting the ’ infront making it become an assignment pattern is wrong, you need 3 items in the pattern.