Triggering Covergroup Sampling via SVA

SystemVerilog
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4

In reply to Have_A_Doubt:

  1. The .triggered can be used as a trigger for the cover group, but this is not going to work in this case because the framelength is computed within the sequences, and it’s value needs to be copied to the module variable.
  2. The reason Display statement "1st cnt at … " executes multiple times is because at every clocking event (the posedge clk) you start a new independent thread for the evaluation of the sequence Detect_EOP.
  3. On the multiple times, the issue is that you have a new thread at every clocking event.
# KERNEL:  1st cnt at 5 // First thread
# KERNEL: Property  PASSes  at  15 // 2nd new thread is vacuous (not a $rose(SOP))
// The PASS action block is displayed, assertion is vacuously TRUE
# KERNEL: Property  PASSes  at  25  // 3rd new thread is vacuous
# KERNEL: Property  PASSes  at  35  // 4th new thread is vacuous
# KERNEL: Property  PASSes  at  45  // 5th new thread is vacuous
# KERNEL: cnt is 1   // First thread is nonvacuously TRUE
// "cnt is 1" message is not the same as "1st cnt at" message
# KERNEL: Property  PASSes  at  55 // First thread passes nonvacuously
# KERNEL: Property  PASSes  at  55 // ?? don't know why the repeat here
#

Read my paper Understanding the SVA Engine (item 3 below)
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…

  1. SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats | Verification Academy
  2. Free books: * Component Design by Example FREE BOOK: Component Design by Example … A Step-by-Step Process Using VHDL with UART as Vehicle | Verification Academy
  1. Papers:

Udemy courses by Srinivasan Venkataramanan (http://cvcblr.com/home.html)
https://www.udemy.com/course/sva-basic/
https://www.udemy.com/course/sv-pre-uvm/