Triggering Covergroup Sampling via SVA

In reply to ben@SystemVerilog.us:

Thanks Ben ,

Need a little help with the following code :: Seq_Triggered

I observe the following ::

(1) Display statement "1st cnt at … " executes multiple times whereas the expectation is for it to be executed only once

(2) Although cnt is 5 , bin auto[0] is covered i.e value of framelength of 0 is being hit instead of value 5 .

**( Using  event  triggering  bin auto[5]  is  covered  )**