Tracing back the 'x value generated by a variable

SystemVerilog
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1

Hi,

I am trying to find out why the value of clkout variable is 'x , From the figure below which variable should I examine next?(s or clk2)

assign clkout = (s==1’b1)? clk1 : clk2

Value of s is X, value of clk1 is 0 and value of clk2 is X
img

Thanks

2

In reply to sj1992:

Both signals contribute to clkout being 'x. Only you or the designer would know what the signals should have been.

3

In reply to dave_59:

Thanks Dave.