Toggle a force signal inside OVM sequence

Hello everyone,

I have a in my TB

initial begin 

force DUT_TOP_INST.vt =0;
 #300ns;
force DUT_TOP_INST.vt =1;

end

Now i want to control this vt pad in my ovm_sequence how do i do that. I want to toggle it basically
Can i override force signal ??


Thanks in advance !

In reply to tejasakulu:

I believe you can apply the concepts in this paper to the OVM.

In reply to dave_59:

Thanks dave for reply. But i cannot override a force until i call release right? So i need to release it and then i can toggle; with force being on if i try to override it doesn’t work
Correct me if i’m wrong

Thanks

In reply to tejasakulu:

One should never use force/release statements. BAD practice because of which you are running into the troubles. Use an interface and handle to the interface to manipulate the signals of those interfaces. I did a quick scan of white paper and describes the solution to your problem aptly.
-anil

In reply to tejasakulu:

Another force on a signal replaces an existing force—there’s no need to release it first.

Also, there’s no need to force to a literal constant. You can do

bit vr_reg;
initial force DUT_TOP_INST.vt =vr_reg;
initial begin
 #300ns;
 vr_reg = ~vr_reg;
end

That way you can set up a driver to modify the value of vr_reg directly.

In reply to dave_59:

Thanks Dave

So you mean to say :

module testbench_top
bit vr_reg;
initial force DUT_TOP_INST.vt =vr_reg;
initial begin
 #300ns;
 vr_reg = ~vr_reg;
end

interface test;
logic a;
endinterface

class driver;
virtual test vif;
new = ()
task test();
vif.vr_reg =1 ;
#200ns
vif.vr_reg = 0;
endtask

Let me know if this what you meant "setup the driver to modify the value of vr_reg"

Thanks

In reply to tejasakulu:

You need to get rid of force statements and initial blocks. You can look at the following example in

$QUESTA_HOME/examples/systemverilog/interfaces/controller

DUT_TOP_INST.vt should be part of your interface signals to drive or sample.

You are almost there. keep at it.
-anil