Toggle a force signal inside OVM sequence

OVM
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6

In reply to dave_59:

Thanks Dave

So you mean to say :

module testbench_top
bit vr_reg;
initial force DUT_TOP_INST.vt =vr_reg;
initial begin
 #300ns;
 vr_reg = ~vr_reg;
end

interface test;
logic a;
endinterface

class driver;
virtual test vif;
new = ()
task test();
vif.vr_reg =1 ;
#200ns
vif.vr_reg = 0;
endtask

Let me know if this what you meant "setup the driver to modify the value of vr_reg"

Thanks