Timing Assertions

SystemVerilog
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2

In reply to Husni Mahdi:

  1. You need the $rose(valid). I don’t see any issue with your assertion. On your TB, I prefer to use nonblocking assignments as a style, though the model would work.
  2. $rose(valid) |-> valid // at $rose(valid) valid==1, thus the valid in the consequent is not needed

task run();
        @(negedge clk) valid <= 1; 
// the valid=1 works because signals are sampled and 
//   use the values of the Preponed region of the time stamp.
        repeat ($urandom_range(1,4)) begin 
            @(negedge clk);
        end 
        ready <= 1;
        @(negedge clk) ready <= 0; valid <= 0;
    endtask
 
property RUN;
        @(negedge clk) $rose(valid) |-> ##[6:10] $stable(valid) && ready;
    endproperty

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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    Understanding and Using Immediate Assertions
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