[SystemVerilog] Difference between `wait(cb.signal == 1'b1)` and `@(cb iff cb.signal == 1'b1)`

SystemVerilog
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In reply to dave_59:

Hi Dave,

I have tried to simulate example provided by you and below is result.
I wanted to understand below behavior.


  # wait(cb.v)              20
  # @(cb)                   30
  # @(cb iff !cb.v)         40
  # @(cb)                   50
  1. As, we know “wait” is level sensitive will be block until cb.v = 1 ( and will continue check ).
  2. Clocking block input will be stable( prepone region ) before clocking event.

So, as v is updated at #12. but as you mentioned which region sampled value will update for #20 clocking event is not define by 1800.
but , wait is level sensitive it will become true as soon as cb.v updated ( display come at #20 ).
So, in which condition below display will come at #30 instead of #20.


  # @(cb)                   30

as per me this behavior, due to “clocking event @(cb)” evaluate before “wait” for #20 time.
hence,@cb $display(“@(cb)”, $time); shift to next time clocking event.
is it correct understanding ?

Thanks!