[SystemVerilog] Difference between `wait(cb.signal == 1'b1)` and `@(cb iff cb.signal == 1'b1)`

In reply to No:

I strongly suggest when you have a process using clocking block events, use only clocking events in that process, and no other event controls.

Although the LRM guarantees that clocking block input variables get updated before triggering the clocking block event, it says nothing about which region the input samples get updated. This is best illustrated if you have @(cb) as the next event control after thewait (cb.valid …).

module top;
  bit clk=1, v;
  clocking cb @(posedge clk);
    input v;
  endclocking
  always #5 clk= !clk;
  
  initial begin
    wait(cb.v) $display("wait(cb.v)",, $time);
    @cb $display("@(cb)",, $time);
    @(cb iff !cb.v) $display("@(cb iff !cb.v)",, $time);
    @(cb) $display("@(cb)",, $time);
    $finish;
  end
  
  initial begin
    #12 v = 1;
    #26 v = 0;
  end
endmodule

On some simulators you will see that the wait followed by @cb occurs in the same cycle, whereas @(cb) followed by @(cb) always comes comes in adjacent cycles.