Systemverilog assertion

SystemVerilog
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1

Hello I’m working on assertion macro for the first time and trying to write the following assertion But I’m facing an error Illegal macro instance syntax at the `assert line. I’m passing “data” as the argument that needs to be substituted in place of in_data in the macro. Please help!

define assert_in_data_not_unknown_p(in_data) \ property ``in_data``_not_unknown_p(in_data); \ @(posedge clk) disable iff(rstn) \ !$isunknown(in_data); \ endproperty \ \ assert property (``in_data``_not_unknown_p(in_data)) begin uvm_info(“PROPERTY”,$sformatf(“in_data data:%0h”,in_data) ,UVM_NONE) end else begin`uvm_error(“PROPERTY”,$sformatf(“in_data data:%0h”,in_data) end;

`assert_in_data_not_unknown_p(data)

2

In reply to Nimisha Varadkar:
Why are you using a `define?
Use a SystemVerilog checker instead.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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3

In reply to ben@SystemVerilog.us:

I have use the assertions across multiple blocks, so it needs to be as a macro only and not checker.

4

Is there anything I’m missing out in the syntax or is it because of the usage of `uvm_info which itself is a macro which is causing a problem?

5

In reply to Nimisha Varadkar:
Am I missing something here?
A checker can be instantiated within a block or it can be bound to a block.

Am not a fan of the `define, too many `` (not sure about the meaning).

Try to explore the use of checker.
Ben systemverilog.us

6

For reference, the problem was due to the $sformatf, it can be resolved by using $psprintf instead.

7

In reply to Nimisha Varadkar:

This is interesting since $psprintf isn’t part of the LRM. I think there are other underlying issues that you aren’t addressing.