In reply to ben@SystemVerilog.us:
Hi ben,
I understand the behavior of throughout.
Thankfully… so I tried to another example.
property CHK02;
@(posedge clk)
$rose(idle) |=> stable(!reset) throughout (idle [*0:] ##1 !idle ##1 idle);
endproperty
CHK02_P : assert property (CHK02);
But this makes fail at 23NS. Could you give me a clue for resolve this?