In reply to rgarcia07:
Several issues with your assertion:
a[*first_hi] ##0 $fell(a) // using "a" instead of signal
//This sequence is always a no match, regardless of the values of the repeat.
//For simplicity, let first_hi==1. Now you have as a sequence
(a[*1] ##0 fell(a) // or more simply
a ##0 fell(a) // and that says that in the very SAME cycle, a==1 and a==0
// What you need is
a[*first_hi] ##1 $fell(a)
// Your property would then read
property double_beat_signal_check(clk, areset_n, signal, first_hi, first_low, second_hi, second_low);
@(posedge clk) disable iff(!areset_n)
$rose(signal) |-> signal[*first_hi] ##1 $fell(signal) ##1 !signal[*first_low]
##1 $rose(signal) ##1 signal[*second_hi]
##1 $fell(signal) ##1 signal[*second_low];
endproperty
- A second issue is that depeding upon the values of the repeats, a 2nd attempt of the assertion may fail. An attempt ocurs at every $rose(a) in this property. For example:
// assertion $ose(a) |-> a[*2] ##1 !a[*3] ##1 a[*1] ##1 !a[*1]
a 000011111111100000000000011110000
clk | | | | | | | | | | | | | | | |
Attempt1 ^
count a==1 1 2 1 P // assertion pases
count a==0 1 2 3 1
----
Attempt2 ^
count a==1 1 F // assertion FAILS, a[*2] failed
count a==0 1 2 3 1
If you want the assertion to trigger once, use the model (my reply) at
https://verificationacademy.com/forums/systemverilog/system-verilog-assertion-2
You ca also use the action block to reset that block to zero for pass or fail at the ed of a triggered assertion.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
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- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
- SVA Alternative for Complex Assertions
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- SVA in a UVM Class-based Environment
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