How to assert only once?
In reply to Abhisek sarkar:
How to assert only once?
initial begin
#20ns; // or some other wait statement if needed
Ap_myassertion: assert property{...};
end
Ben systemverilog.us
In reply to Abhisek sarkar:
In reply to ben@SystemVerilog.us:
I mean it will execute only once?
Yes. See 16.14.6 Embedding concurrent assertions in procedural code. Or you can use an immediate assertion if you just need to check a boolean expression.
In reply to dave_59:
Another approach is to use a module variable to enable the assertion. Within the assertion, a successful antecedent calls a function to change the value of that variable.
bit clk, a, b, c, block=0;
// If antecedent matches, assertion is fired once,
// NO other assertions to be refired.
function automatic void set_block(bit x);
block = x;
endfunction
ap_once: assert property(@ (posedge clk)
!block ##0 $rose(a) ##1 (b, set_block(1'b1)) |->
strong(##[1:$] c)) ;
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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