System Verilog typing warning.This assignment is a violation of SystemVerilog strong typing rules for enumeration datatypes

SystemVerilog
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1

HI,
While running a test I get this warnings in my log file . port0.speed = speed_port0;
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ncvlog: *W,ENUMERR (/ws/users/m/mshah/thornham/manav_trial_repo/verif/mac.hg/sv/uvm/sv/nome_mac_serial_led_ref_model.sv,447|28): This assignment is a violation of SystemVerilog strong typing rules for enumeration datatypes.

I have a sequence item class where I have declared this enum

class nome_mac_serial_led_trans extends nome_base_sequence_item;

// Enums
typedef enum bit[2:0] {LED_SPEED_10M = 0,
LED_SPEED_100M,
LED_SPEED_1G,
LED_SPEED_10G,
LED_SPEED_25G,
LED_SPEED_40G,
LED_SPEED_50G,
LED_SPEED_100G
} nome_mac_serial_led_speed_e;
rand nome_mac_serial_led_speed_e speed;

and I have created instance of this class in reference model where I use it as follows.
port0= nome_mac_serial_led_trans::type_id::create(“port0”,this);
port0.speed=speed_port0;

I get that warning for the above line. Can you help whats wrong in this.?

2

In reply to manavshah33:

What is “speed_port0” here?

3

In reply to janudeep3:

@Anudeep_J

speed_port0 is one of the temporary register I created and I am passing its value to the sequence item class port0.

4

In reply to manavshah33:

And what is the type of speed_port0? Is something other than nome_mac_serial_led_speed_e?

5

In reply to dave_59:

speed_port0 is just temporary variable , it is declared as
logic [2:0] speed_port0;

6

In reply to manavshah33:

Yo need to declare it as

nome_mac_serial_led_speed_e speed_port0;

or you need an explicit cast

port0.speed = nome_mac_serial_led_speed_e'(speed_port0);