Verification Academy
System Verilog typing warning.This assignment is a violation of SystemVerilog strong typing rules for enumeration datatypes
SystemVerilog
strong-typing-rules
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enumeration-datatype
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warning
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SystemVerilog
Anudeep_J
February 9, 2016, 6:54am
2
In reply to
manavshah33
:
What is “speed_port0” here?
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