System Verilog coverage

Coverage
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1

Hello everyone, I want to hit my bins once, and then I don’t want to hit that bin repeatedly. Can you help me?

eg.

covergroup tx_frame_check  @(posedge vif.gtx_clk);

        cp_sfd : coverpoint tr_h.SFD

        {
            bins sfd_bins = {8'hab};
        }
endgroup

I want to hit sfd_bins bins once, and then I don’t want to hit that bin repeatedly. But the triggering event should be posedge of clock only Can you help me?

2

In reply to dyno:

Why? By default a bin gets covered by hitting it once. Extra hits are irrelevant.

3

In reply to dave_59:

I have to clarify a question I have because I’m new to the verification field: Does it matter how many times I hit the bins?

4

In reply to dyno:

Depends on what your testing requirements are, but usually one hit is good enough. The default at_least covergroup option is 1 hit for s bin to be considered covered. But tools may still keep counting hits for debug usage.

5

In reply to dave_59:

so is there any way to stop the counting of hits ?

6

In reply to dyno:

Why? It won’t affect the overall coverage calculation. And it won’t help performance. The most effort goes into figuring out which bin needs to be hit. Adding another check to see if the counter needs to be disabled might just add to the effort.