System Verilog Concurrent Assertions

SystemVerilog
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In reply to fenil_shah:
I strongly suggest that you read my papers below as they address the concept of attempt and threads.
Your “assert (@(posedge clock) req ##[4:32] gnt )” is incorrect; You meant a concurrent assertion, like
assert property (@(posedge clock) req ##[4:32] gnt ); For this, you can say:

  • At every clocking event you have an attempt, if req==0 the assertion fails
  • If for every successful attempt (req==1) gnt==1 4 to 32 cycles later, then the assertion passes, else it fails.
  • Every attempt is separate and independent from other attempts, and each attempt has a life of its own. You can think of it as blowing soap bubbles; at every clocking event you emanate a new bubble, and that bubble has a life of its own.

You need to understand the concept of vacuity, and threads; my papers explain those concepts.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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