System verilog assertion

SystemVerilog
,
1

hi i am writing assertion like this for clock check but assertion getting failed only initially once for all the four property , that’s why i am tried using disable iff condition which commented here but i am facing below compilation issue when i used disable if could you please help me to resolve or avoid initial assertion issue or disable iff compilation issue
error:
Error-[EWSENATE] Expression with side effects
/proj/br_ccd_dft_ver1_nobackup/users/abhich/gn-972038/ccd/src/test/tools/dft/env/clock_stop_chk.sv, 50
ccd_clock_check, “(v = $realtime)”
Expressions with side effects not allowed in temporal expressions.
Expression: “(v = $realtime)”

property p_local_clk1_hi; 
	  realtime v; 
	//  @(posedge local_clk1) disable iff ((!enable)|(!reset)) (v=$realtime) |-> @(negedge local_clk1) ($realtime-v)==TON_local_clk1;
      @(posedge local_clk1) (enable, v=$realtime) |=> (($realtime-v)/2)==TON_local_clk1;
endproperty 
ap_local_clk1_hi: assert property (p_local_clk1_hi)  $display("ap_local_clk1_high property running properly with using enable");
                                                     else $error( "assertion Error: TON_local_ckl1 is not matching. Ton_local_clk1 =%t",TON_local_clk1);


property p_local_clk1_lo; 
	  realtime v1; 
	//  @(negedge local_clk1) disable iff ((!enable)|(!reset)) (v1=$realtime) |-> @(posedge local_clk1) ($realtime-v1)==TOFF_local_clk1;
      @(negedge local_clk1) (enable, v1=$realtime) |=> (($realtime-v1)/2)==TOFF_local_clk1;
	endproperty 
ap_local_clk1_lo: assert property (p_local_clk1_lo);

property p_local_clk2_hi; 
	  realtime v2; 
//	  @(posedge local_clk2) disable iff ((!enable)|(!reset)) (v2=$realtime) |-> @(negedge local_clk2) ($realtime-v2)==TON_local_clk2;
        @(posedge local_clk2) (enable, v2=$realtime) |=> (($realtime-v2)/2)==TON_local_clk2;
endproperty 
ap_local_clk2_hi: assert property (p_local_clk2_hi);

property p_local_clk2_lo; 
	  realtime v3; 
//	  @(negedge local_clk2) disable iff ((!enable)|(!reset))(v3=$realtime) |-> @(posedge local_clk2) ($realtime-v3)==TOFF_local_clk2;
    @(negedge local_clk1) (enable, v3=$realtime) |=> (($realtime-v3)/2)==TOFF_local_clk2;
	endproperty 
ap_local_clk2_lo: assert property (p_local_clk2_lo);
2

SystemVerilog doesn’t allow direct assignment to local property variable inplace of property expression.

Means writing statement directly like v = $realtime is invalid syntax, proper syntax is to write a expression with statement, and when expression becomes true it will sample as per that statement.

In your case:


@(posedge local_clk1) disable iff ((!enable)|(!reset)) (enable, v=$realtime) |=> ((($realtime-v)/2)==TON_local_clk1);

or


@(posedge local_clk1) disable iff ((!enable)|(!reset)) (1, v=$realtime) |=> ((($realtime-v)/2)==TON_local_clk1);

Above both are same in your case.

3

In reply to Ronak Bhatt:
realtime v;
(posedge local_clk1) disable iff ((!enable)|(!reset)) (v=$realtime) |-> @(negedge local_clk1) ($realtime-v)==TON_local_clk1;

i wanted check above thing my code but i could not able to sample v = $realtime its showing syntax error as you said , so any other way i can sample the v in my property or any other way i can write my property , because if am not use the disable iff i will get initially assertion error (when enable and is low);

4

In reply to Abhilash c h:

You need to describe when you want to sample the value through an expression. In your code you have written “(v=$realtime)” without any expression.

For your case, You can take either enable or 1 as your expression.

@(posedge local_clk1) disable iff ((!enable)|(!reset)) (enable, v=$realtime) |=> ((($realtime-v)/2)==TON_local_clk1);

5

In reply to Ronak Bhatt:

it’s working
Thanks Ronak Bhatt .