SystemVerilog doesn’t allow direct assignment to local property variable inplace of property expression.
Means writing statement directly like v = $realtime is invalid syntax, proper syntax is to write a expression with statement, and when expression becomes true it will sample as per that statement.
In your case:
@(posedge local_clk1) disable iff ((!enable)|(!reset)) (enable, v=$realtime) |=> ((($realtime-v)/2)==TON_local_clk1);
or
@(posedge local_clk1) disable iff ((!enable)|(!reset)) (1, v=$realtime) |=> ((($realtime-v)/2)==TON_local_clk1);
Above both are same in your case.