System verilog assertion

In reply to Abhilash c h:

You need to describe when you want to sample the value through an expression. In your code you have written “(v=$realtime)” without any expression.

For your case, You can take either enable or 1 as your expression.

@(posedge local_clk1) disable iff ((!enable)|(!reset)) (enable, v=$realtime) |=> ((($realtime-v)/2)==TON_local_clk1);