System Verilog Assertion - SVA - All the ones on the data bus should be contiguous

SystemVerilog
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9

In reply to Geethanand Nagaraj:
The generate is expanded at elaboration not in simulation.
My previous property did not consider the case of a “10” sequence like 000111100000 //pass
The following does it because the loop detects that 10 case, and considers it in evaluating the return value. Hopefully, I was correct in my evaluations.


   function automatic bit contig (bit[15:0] x);
      bit gota1, gota10;
      for (int i=15; i==0; i--) begin 
        case ({i==0, gota10, gota1})
         3'b000: if(x[i]==1'b1) gota1=1'b1;  // new '1'
         3'b001: if(x[i]==1'b0) gota10=1'b1; // there was a 1, new 0
         3'b010: if(x[i]==1'b1) return 0; // was a 10, now new 1 -> error 
         3'b011: if(x[i]==1'b1) return 0; // was a 10, now new 1 -> error 
         3'b100: return 1; // last bit, x==0 -> OK, no error 
         3'b101: return 1; // was a 1, NO 10, x==0000000...10 or x==000000...11-> OK 
         3'b110: if(x[i]==1'b1) return 0; // was a 10, now new 1 -> error 
                 else return 1; // was a 10, now new 0 -> OK 
         3'b111: if(x[i]==1'b1) return 0; // was a 10, now new 1 -> error 
                 else return 1; // was a 10, now new 0 -> OK 
          
        endcase
        /* if(!gota1 && x[i]==1'b1) gota1=1'b1;
        else if(gota1 && x[i]==1'b0 ) return 0; 
        else if(i==15 && (!gota1 || x[i]==1'b1)) return 1; */ 
      end
   endfunction

   property p_contig; 
    bit[15:0] v;
     @ (posedge clk) $rose(a) |-> (1, v=contig(q))  ##0 v;  
   endproperty 
   ap_contig: assert property(@ (posedge clk) p_contig);

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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